1. Field of the Invention
The present invention relates to a signal processing device having functions such as varying a level of an audio signal.
2. Description of the Prior Art
FIG. 11 is a circuit diagram showing a prior art audio signal processing apparatus SPAO. The signal processing apparatus SPAO is comprised of discrete ICs and passive elements; that is, the signal processing apparatus SPAO generally consists of an input buffer B1, an output buffer B2P, an electronic volume circuit 100P, and a differentiating circuit. The differentiating circuit consists of a capacitor 22 and a resistance 15.
The electronic volume circuit 100P is a digital IC consisting of a ladder resistance 4P and an analog switch group 3P; the ladder resistance 4P has n resistances, R.sub.1 to R.sub.n, and the analog switch group 3P has n analog switches, S.sub.1 to S.sub.n.
When the above-mentioned electronic volume circuit 100P is used in an audio circuit, the analog switch group 3P is comprised of elements each having a CMOS structure, namely, so-called transmission gates. FIG. 4(b) depicts a symbolized transmission gate circuit with a symbolized switch SW (FIG. 4(a)). The switch SW of FIG. 4(a) is equivalent to each of the analog switches, S.sub.1 to S.sub.n, shown in FIG. 11. FIG. 5 depicts a control circuit of the transmission gate, and FIG. 6 depicts its internal equivalent circuit. Either of the circuits is a well-known basic circuit.
In general, several tens of the electronic volume circuits 100P each consisting of the transmission gate SW group 3P and the ladder resistance 4P are connected in series, and each of the switches arbitrarily turns ON/OFF, thereby each electronic volume circuit 100P functions as a variable resistance. The switch group 3P is fabricated according to a system design where a digital signal control by a micro computer or the like allows the switches, S.sub.1 to S.sub.n, to operate. Specifically, the so-called up-down switches work like a manual type mechanical volume to sequentially raise or drop an attenuation level.
On the other hand, the input buffer B1 is comprised of an operational amplifier 1, a capacitor 21 and a resistance 11. The capacitor 21 performs a.c. coupling. The operational amplifier 1 buffers an input signal V.sub.1 to the electronic volume circuit 100P without attenuation caused by impedance mismatching. D.C. bias voltage V.sub.cc /2 is applied via the resistance 11 to a positive (+) input terminal of the operational amplifier 1. The d.c. bias voltage V.sub.cc /2 is produced by a bias circuit BiP. For example, voltage dividing resistances 130 and 140 are placed between supply voltage V.sub.cc and the ground GND so that the d.c. bias voltage V.sub.cc /2 is produced. An electrolytic capacitor 24 permits the flow of alternating current from a junction at V.sub.cc /2 (a node between the resistances 130 and 140) to ground it.
The output buffer B2P is comprised of an operational amplifier 20 and a resistance 120. The operational amplifier 20 buffers an output signal V.sub.3 (signal at a node N.sub.30) from the electronic volume circuit 100P to an output terminal N.sub.4 without attenuation so that an output signal V.sub.4 can be produced, not being affected by input impedance of a subsequent stage circuit connected to the output terminal N.sub.4. Similarly, the d.c. bias voltage V.sub.cc /2 is applied to a positive (+) input terminal of the operational amplifier 20.
The operational amplifiers 1 and 20 arc analog ICs having a bipolar configuration.
Various disadvantages arise because of the above-mentioned configuration in the prior art signal processing apparatus.
FIG. 12 is a circuit diagram illustrating in detail an internal structure of the operational amplifier 20 shown in FIG. 11. As can be seen, a differential circuit equivalent to an input unit of the operational amplifier 20 is comprised of bipolar transistors Q.sub.1 and Q.sub.2. A resistance R.sub.B is represented as a variable resistance in an aspect that a resistance value at the ladder resistance 4 varies.
However, since the differential circuit of the input unit is comprised of the bipolar transistors Q.sub.1 and Q.sub.2, base current I.sub.B flows from its positive (+) input terminal to the variable resistance R.sub.B to cause voltage drop represented by I.sub.B.R.sub.B. A signal V.sub.3 (voltage drop I.sub.B.R.sub.n) varies according to time-varying value of the resistance R.sub.B as the analog switch group 3P sequentially operate. Variations in the signal V.sub.3 is shown in FIG. 13(a).
A waveform representing d.c. change in the signal V.sub.3 is shaped as shown in FIG. 13(b) by a differentiating circuit consisting of a capacitor 22 and a resistance 15. In addition to that, a resistance and a capacitor in a subsequent stage circuit like a power amplifier are arranged to constitute an integrating circuit 50 as shown in FIG. 7. As a result, a waveform of an output signal V.sub.4 (V.sub.out) is smoothed by the integrating circuit 50, and an output signal V.sub.INT therefrom is a cause of noise (click noise) offending the ear.
The prior art signal processing apparatus is configured in such an arrangement that two discrete elements, namely, the electronic volume circuit 100P and the operational amplifier 20, are wired, and hence, floating impedance Z.sub.ST appears between those elements (100P and 20) (see FIG. 12). Since the base current I.sub.B also flows in the floating impedance Z.sub.ST, variations in the output signal V.sub.3 are further complicated. Thus, the floating impedance Z.sub.ST is also a cause of the generation of the click noise.
Disadvantages as mentioned above arise not merely in the signal processing apparatus SPAO but are generally caused in using electronic volume ICs.